1. Field of the Invention
This invention relates to a semiconductor memory device, such as a dynamic random access memory (DRAM), in particular, precharge thereof.
2. Description of the Related Art
A DRAM receives an external command signal for precharging bit lines with word lines inactivated generally, that is, a precharge command signal. Therefore, the DRAM has a pin or a pad which receives precharge command signals.
Conventional DRAM has an address buffer circuit, a command buffer circuit, and a memory cell array in which a plurality of memory cells are arranged in rows and columns. The address buffer circuit receives an address signal, and outputs an internal address signal. The command buffer circuit receives a precharge command signal, an active command signal, a refresh command signal, and a write/read command signal in accordance with a clock signal, and outputs an internal precharge command signal, an internal active command signal, an internal refresh command signal, and an internal write/read command signal corresponding to the respective received command signals. The precharge command signal is a command for performing precharge of bit lines, and the active command signal is a command for activating the rows. The refresh command signal is a command for performing refresh of the memory cells, and the write/read command is a command for performing writing/reading of data. The memory cell array receives an internal address signal from the address buffer circuit in response to each of the internal command signals supplied from the command buffer circuit, selects a required memory cell, and performs an operation such as writing or reading of data.
As described above, the DRAM receives various command signals in accordance with a clock signal CLK. Among the command signals, a precharge command signal PRC is important for in timing control in the DRAM.
In the meantime, with increase in the operation speed of the DRAM, it becomes difficult, for lack of time, to input all external commands in accordance with a clock signal CLK.
Specifically, as shown in FIG. 9, if time tRC from an active command signal ACT to the next active command signal ACT is sufficiently longer than a cycle of the clock signal CLK, the DRAM has a sufficient time to operate. Therefore, the DRAM can receive a precharge command PRC between the active command signal ACT and the next active command signal ACT.
However, as shown in FIG. 10, if the time tRC is relatively short with respect to the cycle of the clock signal CLK, it is difficult to externally input the precharge command signal PRC in the DRAM. In FIGS. 9 and 10, WL[0] shows an operation of a selected word line.
Therefore, it has been considered controlling precharge timing inside the DRAM, without externally inputting a precharge command signal PRC. However, as shown in FIG. 10, it is necessary to automatically control to start precharge between an active command signal ACT and the next active command signal ACT. Although a timer is required to perform such a control, it is difficult to manufacture a timer having a high accuracy. Therefore, it is difficult to accurately control precharge start timing, and it is desired to provide a semiconductor memory device which can accurately control the precharge timing.